The present invention relates generally to dynamic random access memory (DRAM) devices and, more particularly, to a system and method for direct write to DRAM using PFET bit-switches.
Existing dynamic random access memories (DRAMs) are generally slower to access than static random access memory (SRAM) or read only memory (ROM). Conventionally, DRAMs gave been manufactured as xe2x80x9cstand alonexe2x80x9d, integrated circuit chips that store large quantities of data for faster access than magnetic or optical disc media, at relatively low prices and lower power consumption. SRAMs and ROMs, by contrast, have usually provided faster access than DRAMs, but often at higher prices and higher power consumption since these memory types require a larger device count per stored data bit, which adds to cost and density.
More recently, interest has increased in using DRAMs as one of several elements of an integrated circuit, such as in an application specific integrated circuit (ASIC) that may include logic or other processing devices in addition to memory. Such DRAM devices in this context are also referred to as embedded DRAM or eDRAM. The goals of using embedded DRAM include obtaining potentially large amounts of easily rewriteable storage with fast access times, but at lower cost and power consumption than SRAMs. One problem associated with existing DRAM architectures is that it takes longer to write a memory cell with a new data bit (e.g., from logic xe2x80x9c0xe2x80x9d to xe2x80x9clogic 1xe2x80x9d or vice versa) than it takes to read or refresh the data bit in that memory cell. This longer write time in turn limits the cycle time or frequency that the DRAM can operate.
One approach taken in writing early within a memory cycle is to hold only one of either a true bit-line or the complementary bit-line at a precharge potential (e.g., ground), while setting a sense amplifier. The sense amplifier (for read or refresh) amplifies a small voltage difference between the true bit-line and the complement bit-line to predetermined high and low voltage logic levels in order to write a data bit to the cell. For write operations, one side (true or complement) of the sense amplifier is held to the precharge level, forcing the sense amplifier to a known state independent of the previously written data to that address. Furthermore, the bit-lines are precharged to a fixed potential in a conduction path through the bit-switches, rather than through local precharge devices at the sense amplifier. To write, bit-switches and write path transistors apply the fixed potential to either the true bit-line or the complement bit-line. The bit-switches on other memory cells not being written are non-conductive so as to isolate those other memory cells when setting the sense amplifiers, such that the stored contents thereof are refreshed (i.e., written back) at the same time the selected memory cell is written. Additional details regarding this early write approach may be found in U.S. Pat. No. 6,400,629 to Barth, et al. (the ""629 patent), assigned to the assignee of the present application and incorporated herein by reference.
Although the early write patent improves upon the write portion of the cycle time by not having to wait until completion of signal amplification in the sense amplifiers, there is still a limit to the cycle time in writing opposite data as reflected by the signal development portion of the write cycle. Since the written cell starts at the precharge level, it will still take longer to write-back than a refreshing cell since the refreshing cell will not completely discharge prior to amplification. Accordingly, it would be desirable to be able to further improve the speed at which data is written by not having to wait for signal development in the first place.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a control circuit for a memory array device having one or more memory storage cells associated therewith. In an exemplary embodiment, the control circuit includes a true bit-line and a complementary bit-line coupled to the one or more memory storage cells. A sense amplifier is coupled to the true and complementary bit-lines, the sense amplifier being configured to amplify a small voltage difference between the true bit-line and the complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A bit-switch pair selectively couples the bit-lines and said sense amplifier to fan-in circuitry, and is further configured so as to couple the fan-in circuitry to the true and complementary bit-lines prior to the activation of a word-line associated with a selected cell for a write operation thereto. Thereby, the write operation to the selected cell is commenced prior to the completion of time associated with signal development on the true and complementary bit-lines.
In another aspect, a dynamic random access memory array architecture includes a plurality of bit-line pairs coupled to a fan-in node, the plurality of bit-line pairs each including a true bit-line and a complementary bit-line coupled to one or more memory storage cells associated with the memory array. A sense amplifier is coupled to each of the plurality of bit-line pairs, the sense amplifier configured to amplify a small voltage difference between an associated true and complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A plurality of bit-switch pairs is associated with each bit-line pair, the bit-switch pairs configured for selectively coupling the bit-line pairs and the sense amplifiers to the fan-in node. Each bit-switch pair is further configured so as to couple the fan-in node to the bit-line pair associated therewith prior to the activation of a word-line associated with a selected cell for a write operation thereto, thereby commencing the write operation to the selected cell prior to the completion of time associated with signal development on the bit-line pair.
In still another aspect, a method for implementing a direct write operation to a selected storage cell of a dynamic random access memory (DRAM) device includes activating a bit-switch pair so as to couple a bit-line pair to a fan-in node prior to activation of a word-line associated with the selected storage cell. The bit-line pair includes a true bit-line and a complementary bit-line coupled to a sense amplifier, the sense amplifier being configured to amplify a small voltage difference between the true and complementary bit-lines to a full level signal at predetermined high and low logic voltage levels. Once the word-line associated with the selected storage cell is activated, the write operation to the selected cell is commenced, prior to the completion of time associated with signal development on the true and complementary bit-lines.